This invention relates to a vector processing unit in which a plurality of successive elements of a vector can be read out from a vector register simultaneously in one machine cycle and can be written into the vector register simultaneously in one machine cycle, said vector processing unit being capable of executing compression transformation and extension transformation of a vector efficiently with simplified hardware.
Generally, a vector processing unit has processing devices of various types, vector registers, and a controlling device and executes various kinds of vector commands. For example, a vector addition command has the following format: VAD, R1, R2, R3, M. In this format, a vector A (A =a.sub.0, a.sub.1 . . . a.sub.n-1) designated by the second operand designation R2 and a vector B ( B=b.sub.0, b.sub.1 . . . b.sub.n-1) designated by the third operand designation R3 are added, respectively, in the corresponding elements, and the vector C obtained by the addition is written into the vector register designated by the first operand designation R1. In the above-mentioned format, M denotes a mask register, and whether or not the operation is to be executed and whether or not writing into the vector register is to be executed is controlled in accordance with the data in the mask register.
In general, as vector commands, there are a vector addition command, a vector multiplication command, a vector subtraction command, a vector store command, a vector load command, and the like. Besides, there may be used a vector compression command and a vector extension command. These two vector commands are very useful when a vector to be processed has a large number of elements, most of which are null.
The vector compression command has the following format:
VCP R1, R3, M PA1 VEX R1, R3, M
and the vector extension command has the following format:
FIG. 1 illustrates compression transformation of a vector, in which M denotes a mask register, VR(3) denotes the vector register designated by the third operand designation R3, and VR(1) denotes the vector register designated by the first operand designation R1. In compression transformation, the row of elements in the vector register VR(3) and the row of mask elements in the register M are compared, a compressed row of elements in which the elements in the register VR(3) corresponding to the "0" mask elements are removed is formed, and this compressed row of elements is written into the vector register VR(3) beginning with the top element without disrupting the order of the compressed row of elements, as shown in FIG. 1.
FIG. 2 illustrates extension transformation of a vector. In extension transformation, the row of elements in the vector register VR(1) and the row of mask elements in the mask register are compared, and the row of elements in the vector register VR(3) are written into the storage regions of the elements of the vector register VR(1) corresponding to the "1" mask elements of the mask register M without disrupting the order of the extended row of elements, as shown in FIG. 2.
In a vector processing unit of the prior art, when the vector A is read out from the vector register, each one of the elements A.sub.0, A.sub.1, . . . , A.sub.n of the vector A is read out from the vector register successively, and when the vector C is written into the vector register, each one of the elements C.sub.0, C.sub.1, . . . C.sub.n is written into the vector register successively. In the above-mentioned vector processing unit, compression transformation and extension transformation can be executed comparably readily.
However, recently, in order to process a large quantity of data at a high speed, another vector processing unit of the prior art in which a plurality of elements belonging to the same vector are supplied to the arithmetic circuit simultaneously and are written into the vector register simultaneously has been used. In this vector processing unit, compression transformation and extension transformation cannot be executed as readily as in the first mentioned vector processing unit of the prior art. Thus, in the second mentioned vector processing unit, there is the problem of how compression transformation and extension transformation of a vector can be more simply controlled using less hardware.